Chapter 8 - The Theory of Drift Step Recovery Diodes (DSRD)

8.1 - Introduction

In traditional step recovery diodes charge is stored in the diode by means of a nearly steady-state forward current flow. That is, the forward bias exists continuously for times comparable to or longer than the hole and electron lifetimes in the active region. However, the more recent high-power drift step-recovery diode (DSRD) uses a short forward bias pulse to introduce stored charge to the device [Grek85], [Grek89], [Belk94], [Foci96]. Since the pulse width is considerably less than the carrier lifetimes, the charge is concentrated near the junctions, which is desirable for a sharp reverse step recovery. Other more complicated high-power devices have been designed with similar pulsed biasing in mind [Grek83],[Gorb88]. For instance, by using this "reversible injection control" [Grek89] two-terminal functional equivalents of the thyristor have been made, which do not suffer from current localization effects characteristic of three terminal devices. Because of this, these new structures have been shown to be capable of operating at much higher power levels than conventional structures, and as such, it has become more important to examine the nature of the forward transient in the basic p⁺sn⁺ diode structure.

8.2 - The Forward Transient In pin Structures

It is possible to obtain an analytical solution for the forward transient for two cases, those being the p⁺in⁺ structure, where high injection is implicitly assumed, and the p⁺sn⁺ structure if it is assumed that the s layer (either p-type or n-type) is under low injection. Since the devices mentioned above are power devices, the low injection case is not of interest here. The forward current is assumed to be constant for the duration of the transient.

The solution for a rectangular pin structure can be obtained by solving the differential equation [Vars69]

(8.1)

where p(x,t) is the excess hole density, X is the distance normalized to the ambipolar diffusion length L_d, and T is the time t normalized to the lifetime τ.

Equation (8.1) is subject to the boundary conditions [Vars69],[Bend67]

(8.2)

(8.3)

and the initial condition [Vars69]:

(8.4)

where W_L is the width of the I region, normalized by L_d, and J_F is the forward current density. In obtaining (8.3), it has been assumed that neutrality exists in the I region, such that p(X,T) = n(X,T).

Solving (8.1) using Laplace transform methods, subject to (8.2) and (8.3) yields the intermediate solution

(8.5)

which can be rewritten as

(8.6)

Taking the inverse Laplace transform of both sides, under consideration of equation (8.4), yields

(8.7)

or, equivalently,

(8.8)

By using the Laplace transform pair [Spie65],

(8.9)

and integrating both sides of (8.8), the final solution can be obtained:

(8.10)

This solution is considerably simpler and more compact than an equivalent solution presented in [Vars69]. (It should be noted that both equation (8.10) and the solution given in [Vars69] only satisfy the initial condition given in (8.4) in the limit of t 0, not at t = 0. This is because the boundary conditions (8.2) and (8.3) are in fact inconsistent with the initial condition, a fact which is not always appreciated.)

The evolution of p(X,T) is shown for τ = 10 μs, W = 250 μm, J_F = 10 A/cm² in Figure 8.1. (The steady state solution is denoted as p_SS(X)). It is immediately evident that substantial charge injection occurs at both x = 0 (the p⁺i junction) and at x = W (the in⁺ junction) throughout the entire transient.

8.3 - The Forward Transient In psn Structures

If the forward current in a p⁺sn⁺ diode is sufficiently large, the injected carriers will overwhelm the background doping, allowing the analytical results for a pin diode to be used to determine the transient response. This section quantifies the critical current density above which these results can be used. It will be shown below that even for very light doping, the expression derived above rapidly becomes inaccurate.

Figure 8.1. Calculated charge injection in a pin diode during the forward transient, for several different values of t/τ. The horizontal axis is linear, and the vertical axis is logarithmic. Note that substantial charge injection occurs at both junctions throughout the entire transient. p_SS(X) is the steady-state distribution.

Consider a device with a lightly doped n-type middle layer, and assume that quasi-neutrality exists in this layer. Then,

(8.11)

Also assume that the doping in the p⁺ and n⁺ regions is much higher than in the n^- middle region. Then the current at the p⁺n^- junction (x=0) will be almost entirely a hole current, and the current at the n^-n⁺ junction (x=w) will be an electron current. Mathematically,

(8.12)

(8.13)

(8.14)

(8.15)

The transport equations can be written as

(8.16)

and

(8.17)

where V_T is the thermal voltage kT/q. If (8.14) is substituted into (8.16), the electric field at x = W can be found:

(8.18)

and similarly, from (8.13) and (8.17),

(8.19)

This allows the current at either junction to be calculated in terms of the doping and carrier distribution. If (8.19), (8.12) and (8.11) are substituted into (8.16), one obtains

(8.20)

Similarly, using (8.18), (8.15) and (8.11) in (8.17) gives

(8.21)

If the first terms in equations (8.16) and (8.17) are identified as diffusion terms, and written as J_diff, and if we define

(8.22)

then (8.20) and (8.21) can be rewritten in the form:

(8.23)

and

(8.24)

Equations (8.23) and (8.24) show that the balance of the drift and diffusion currents at the junctions is affected by the presence of doping in the middle layer. These two functions are plotted as a function of f in Figure 8.2. As N_D → 0, and hence f → 0, both functions approach the value 0.5, which of course leads to equations (8.2) and (8.3). In other words, the drift and diffusion currents at both junctions in a pin diode are equal. This remains largely true for f < 0.1. As N_D increases, and f increases correspondingly, the current at the n^-n⁺ junction is dominated by a drift current, and the current at the p⁺n^- junction is dominated by the diffusion component. Since the diffusion current at the high-low junction becomes small, dn/dx is also small and very little charge is built up at the high-low junction.

Figure 8.2. Diffusion current as a fraction of the total current, at both junctions. In the limiting case of no middle-layer doping, f = 0 and the diffusion and drift components are equal. For very heavy doping, f → ∞ and the high-low junction current is almost entirely drift current, and the p⁺n junction current is almost entirely diffusion current.

It is straightforward to show that f increases rapidly with N_D, if one considers the time imediately after the beginning of the forward transient current pulse. At this early time, no holes will have yet traveled to the n^-n⁺ junction, so we can write:

(8.25)

The current in the bulk of the middle layer must be ohmic, since little charge has been injected and n>> N_D. Thus, in this region,

(8.26)

If this bulk electric field is assumed to build up from zero over a short distance Δx near the n^-n⁺ junction, then the derivative dE/dx in (8.25) can be approximated as E_bulk/Δx. Then, combining (8.25), (8.26) and (8.22) so as to eliminate n(w,0⁺) yields

(8.27)

An estimate for Δx can be obtained by writing

(8.28)

The value of dn/dx in (8.28) can be estimated from the electron diffusion current. Of course, the diffusion current to total current ratio varies with f, as discussed above. The most interesting case is for f =1, where the diffusion current is 1/3 of J_F, since the diode behaviors for f >> 1 and f << 1 are quite different. The case of f =1 is a "critical" boundary case. Thus,

(8.29)

Then combining (8.26) to (8.29) to eliminate Δx yields:

(8.30)

where

(8.31)

Hence, for current densities substantially larger than J₀ (say J_F > 10 J₀), the diode acts as though it were intrinsic, leading to balanced drift and diffusion currents, and charge injection from both junctions. For current densities substantially less than J₀ (say J_F < 0.1 J₀), the charge injection will be dominated by the p⁺n^- junction, and relatively little charge will be stored at the high-low junction. Since J₀ ∝ N_D^3/2, the critical current density J_F = J₀ (corresponding to f = 1) increases moderately quickly with doping, and the usefulness of the intrinsic approximation becomes restricted for even relatively light doping levels.

Physically, equation (8.22) shows that the condition f(x,t) = 1 corresponds to an injected carrier density of n(x,t) = 2 N_D. Thus, if the forward current is large enough such that n(w,0⁺) >> 2 N_D at the high-low junction immediately after the beginning of the transient (i.e. J_F >> J₀), the diode will act as a pin diode.

The validity of this estimate of J₀ is shown by comparison with MEDICI simulations in Figure 8.3. The hole distribution at t = 60 ns is shown for several values of N_D, and hence J₀ (calculated from (8.31)), with = 10 μs, W = 250 μm, and J_F = 10 A/cm². (Since the time is the same in each case, the total charge in each of the diode structures is approximately equal.) Clearly, the hole distributions for J_F/J₀ equal to (i.e., a pin diode), 100, and 10 are very similar and show significant charge injection from both junctions, as expected. In contrast, the hole distributions for J_F/J₀ equal to 0.1 and 0.01 show injection at the p⁺n junction only, as expected. The curve for J_F/J₀ =1 is an intermediate case, showing some charge injection from the high-low junction, but much less than for the cases with larger J_F/J₀ ratios. These simulations confirm the theoretical results derived above. (It should be noted that the doping corresponding to J₀ is quite small - only 5.6x10¹³ cm^-3.)

Figure 8.3. Simulations calculated using the MEDICI simulator to confirm the validity of the derived expression for J₀. J₀ is calculated from (8.31). For J_F/J₀> 10, the diode behaves like a pin diode, with substantial charge injection at both junctions. For J_F/J₀< 0.1, charge injection occurs exclusively at the p⁺n^-junction. J_F = J₀is an intermediate case. In each case J_F= 10 A/cm², and N_Dis varied to change J₀. In order of decreasing J_F/J₀the corresponding values of N_D are 2.6x10¹², 1.2x10¹³, 5.6x10¹³, 2.6x10¹⁴, and 1.2x10¹⁵ cm^-3.

Equation (8.30) predicts how the charge is injected at short times after the beginning of the transient. Obviously, as time progresses, the value of f(W,t) will change, since substantial charge is stored near the high-low junction in the steady state. The key turning point occurs when injected holes from the p+n junction reach the high-low junction. This of course will increase n(W,t), and increase f(W,t). In other words, double injection occurs [Dean69], and injected charge will rapidly build up at the high-low junction after this time. This time can be estimated by dividing the middle region width W, by the drift velocity, such that

(8.32)

This can be rewritten using (8.26):

(8.33)

where

(8.34)

Figure 8.4 illustrates the validity of this calculation for W = 250 m and J_F = 10 A/cm², for a range of N_D from 10¹⁴ to 5x10¹⁴ cm^-3. The hole concentration is plotted at t = t_di for each particular doping. In each case, the peak injected charge at the high-low junction is just beginning to become significant, reaching a density approximately equal to N_D. (Figure 8.1 shows that the steady state distribution is between 10¹⁶ and 10¹⁷ cm^-3, about two orders of magnitude higher than N_D.)

Of course, even after t = t_di, diodes with J_F < J₀ will still have less charge injected at the high-low junction than diodes with J_F > J₀, but the difference will be less noticeable than for t < t_di.

Figure 8.4. Simulations calculated using the MEDICI simulator. The injected hole density at the high-low junction at t = t_diis shown for several different dopings. In each case, the peak density >>N_D. The charge injected at the high-low junction grows rapidly after t = t_di, due to the onset of double injection.

8.4 - Implications For Pulse Sharpening Diodes Design Theory

The use of drift step-recovery diodes in pulse sharpening applications has been described in [Grek85], [Grek89], [Belk94], [Foci96]. An important characteristic describing the reverse transient of any step recovery diode is the ramp voltage, which is the voltage built up across the diode just before the fast sharpening transient begins. The ramp voltage should be as small as possible to obtain an ideal step waveform. In the DSRD, the fast transient begins when the charge sweeping-out boundary [Bend67] emanating from the p⁺n junction meets the sweeping-out boundary emanating from the high-low junction. If the distance between the p⁺n junction and the meeting point of the sweeping-out boundaries is termed W_Q, the ramp voltage V_RAMP can be found by applying Poisson's equation to the fixed ionized charge and the mobile charge, assumed to be moving at the saturation velocity v_S. Thus,

(8.35)

The voltage developed across the quasineutral region between x = W_Q and the high-low junction will be much smaller than the voltage developed across the p-n junction space charge region [Bend67], and is ignored.

To minimize V_RAMP, it is necessary to minimize W_Q. This implies maximizing |dn/dx| at the p⁺n^- junction such that the charge injected by the forward transient is kept very close to the junction. From the preceding section, we can see that this requires that J_F < J₀. Significant improvement in ramp voltage will occur as J_F is brought down from 10J₀ to J₀/10, and relatively little improvement will occur below this, as suggested by Figure 8.2. For instance, a DSRD designed to operate at 1700 V, with N_D = 10¹⁴ cm^-3, will have J₀ = 24.8 A/cm². For a cross sectional area of 0.3 cm², this corresponds to I₀ = 7.4 A. A diode with these parameters was manufactured and presented in [Grek85], where a value of I_F = 3 A was used. Clearly these values of J_F and I_F fall within the predicted desirable range. Decreasing J_F further would have had the undesirable effect of either increasing the cross-sectional area and the junction capacitance, or increasing the forward pulse width t_F, which has its own limits as discussed below.

The expression derived for J₀ can also be used to estimate the maximum charge consistent with good step recovery action that can be stored in a DSRD. The charge stored in a DSRD during the forward bias pulse is given by

(8.36)

where t_F is the duration of the forward pulse. Grekhov noted in [Grek85] that for the injected charge to remain near the junction, t_F should be much smaller than the diode transit time t_T, where

(8.37)

If we choose

(8.38)

and

(8.39)

(such that the effective characteristic length, L_eff, of the injected carrier distribution is W/10) as reasonable maximum values, the maximum Q₊ can be determined as a function of N_D and W. A more useful exercise is to calculate the reverse transient storage time t_S as a function of V_BR and W, where

(8.40)

where Q_- is the maximum charge that can be removed from the diode during the reverse transient. It is important to note that Q₊ and Q_- are not necessarily the same thing. For a wide-base diode under low injection, the maximum net charge that can be extracted from a diode is Q₊/2 [Lind65]. Similarly, for a narrow-base diode, Q_- = 2/3 Q₊. However, for the high-injection case examined here,

(8.41)

as Belkin and Shulzchenko [Belk94] and Focia et al. [Foci96] have reported experimentally. Grekhov's [Grek85] reported experimental values of Q₊ = (400 ns)(3 A) and Q- = ½ (50 ns)(34 A), resulting in Q_-/Q₊ = 0.71; however computer simulations reported below cast some doubt on the accuracy of this.

The breakdown voltage V_BR can be calculated from [Bali87]

(8.42)

where N_D is in cm^-3. In equation (8.40), it is assumed that the diode is operated just below breakdown, and that the pulse to be sharpened is a linear ramp (hence the average voltage of V_BR/2). To determine the cross-sectional area of the device, the DSRD design equation from [Grek85] is used:

(8.43)

Consideration of equations (8.31) and (8.36)-(8.43), and assuming R = 50 Ω, allows N_D and A to be chosen for a particular V_BR. However, this leaves one unspecified physical parameter, W. Making W large will increase the maximum stored charge Q₊, but it will also increase V_RAMP. Ultimately, computer simulations are required to confirm the proper choice of W. However, for the convenience of calculations, the width W with be normalized as a parameter, called the "width factor", or WF, where:

(8.44)

For WF = 1, W is equal to the width of the depletion region at breakdown [Bali87]. (In (8.44), W is in cm and N_D is in cm^-3.) In other words, for WF=1, the depletion region consumes the entire middle layer at V_BR. For WF > 1, portions of the middle layers are never covered by the depletion region, and for WF < 1 the diode is a punchthrough device. (If a punchthrough structure is used, equation (8.42) no longer applies.)

Consideration of equations (8.34)-(8.44) produces the plot shown in Figure 8.5. The device presented in [Grek85] corresponds to WF = 1.65, and V_BR = 1700 V, for which the ideal t_S is predicted to be about 57 ns. This agrees rather well with the 50 ns value that was used in the experiment. It was reported that the step recovery action degraded noticeably above 50 ns, as one would expect.

Figure 8.5. The curves on this design chart show the maximum practical storage time t_S, in nanoseconds, for a psn diode with a middle-layer width factor WF of 1, 1.65, 2, or 3, and breakdown voltage V_BR (in Volts).

It is apparent from Figure 8.5 that the DSRD structure is of little use below 500 V, as the maximum useful storage times become very short.

Previous design approaches for DSRDs [Grek85] did not specify a simple method of choosing J_F and w. The equations presented above, in the form of (8.31) and Figure 8.5, partially rectify this situation. The equations given above do not guarantee that a given diode structure can be used as a DSRD. Choosing J_F << J₀ ensures that the ramp voltage is minimized as much as possible for a particular structure, but it does not ensure that the ramp voltage is insignificant relative to V_BR. To calculate V_RAMP exactly computer simulations are required. The next section reports the results of such simulations.

8.5 - DSRD Ramp Voltage

To develop a design approach for the DSRD ramp voltage, simulations were performed using the MEDICI device simulator, for fifteen devices. Values of N_D, A, and I_F were determined using the theory presented in the last section for devices with V_BR values of 500 V, 1000 V, 1500 V, 2000 V, and 2500 V. For each of these voltages, three values of WF were considered: 1, 2, and 3. Knowledge of WF allowed t_F and t_S to be calculated for each device.

The results of the transient simulations are very simple. For WF = 1, V_RAMP/V_BR = 0.1, regardless of V_BR. Similarly, for WF = 2, V_RAMP/V_BR = 0.25, regardless of V_BR, and for WF = 3, V_RAMP/V_BR = 0.4, regardless of V_BR. It is not surprising that for a given WF the V_RAMP/V_BR ratio is independent of V_BR, because for each diode with the same WF the shape of the injected charge is identical, if it is normalized to the width of the middle layer. Thus, the normalized position where the sweeping-out boundaries from the left and right meet (initiating the step recovery action) will be identical for diodes with the same WF. Similarly, the normalized width of the depletion region at V_BR is also identical for devices with a given WF, by definition. Thus the ratio of the two positions, and hence the ratio of the corresponding voltages (V_RAMP and V_BR) will be identical.

This considerably simplifies the design of DSRDs. Typically, one wishes to have V_RAMP/V_BR ≤ 0.1, and as large a storage time as possible, so WF = 1 is the ideal choice. With WF fixed, all parameters are now uniquely specified for a given V_BR. With this in mind, Figure 8.5 can be simplified and enlarged, as in Figure 8.6. It is now evident that the DSRD is restricted to high voltages, of at least 1 kV, if V_RAMP/V_BR ≤ 0.1 is to be achieved. Below 1 kV, the storage time becomes too short to work with, as does the forward bias pulse width, t_F.

Figure 8.6. Maximum practical storage time t_S, and the corresponding forward bias time t_F, in nanoseconds, for a psn diode with the ideal middle-layer width factor WF of 1 and breakdown voltage V_BR (in Volts).

8.6 - DSRD Transition Times

Grekhov et al [Grek85] calculated that the maximum voltage rate of change for saturation-velocity limited silicon devices is 2000 V/ns. Since the current density and carrier distributions change radically during the diode reverse transient, it is not possible to sustain the extraction velocity of the carriers at the saturation velocity for the entire step recovery transient, so in practice one can only expect to achieve a fraction of this maximum transition speed. The switching time results (t_R) from some of the simulations described in the previous section (with the addition several high-voltage devices) are summarized in Table 8.1, along with the physical and electric parameters used in the simulations. Table 8.1 shows that the maximum realizable voltage-rate-of-change is about 500 V/ns, which is the approximate maximum value for conventional SRDs and WFSRDs as well (see Table 1.1). (It is not clear why there appears to be a rate-of-change minimum around the 2500 V device.) Also, the low values of τ_EFF at and below 1 kV again show the operating voltage restrictions of the DSRD.

Figure 8.7 shows a typical simulated waveform for the 4000 V device specified in Table 8.1.

Table 8.1 - Switching times for various DSRDs, with WF = 1. τ_EFF is calculated from equation (3.4), using the values in the table.

	Calculated Physical Parameters			Calc. Electrical Parameters			Simulation Results
VBR, V	ND, cm-3	A, mm2	L, μm	IF, A	tF, ns	tS, ns	tR, ns	VBR/tR, V/ns	VRAMP,V	τEFF, ns
500	5.11014	1.75	36.3	2.47	5.5	2.7	1.0	500	50	12.2
1000	2.01014	8.83	81.5	3.11	27.7	8.6	2.1	476	100	59.5
1500	1.21014	22.7	131	3.56	71.2	16.9	3.1	484	150	151
1700	9.91013	30.5	151	3.71	95.4	20.8	3.6	472	170	208
2000	8.01013	44.5	183	3.92	139	27.3	5.5	364	200	292
2500	5.91013	74.9	237	4.22	235	39.7	8.9	281	250	590
3000	4.71013	114.6	293	4.49	359	53.7	7.4	405	300	744
4000	3.21013	224.3	411	4.94	703	86.8	7.8	513	400	1450
5000	2.41013	377.5	533	5.32	1183	126	9.9	505	500	2430

Figure 8.7 - Optimum pulse sharpening action of the 4000 V device described in Table 8.1. The sharpened output 10%-90% rise time is 7.8 ns.

These results do not agree entirely with Grekhov's [Grek85]. In [Grek85], a 1700 V diode was reported with a 1.5 ns rise time, giving a V_BR/t_R ratio of 1133 V/ns. This seems overly fast, compared to the results listed in Tables 8.1 and 1.1. Figure 8.8 shows the results of a Medici simulation reproducing the conditions described in [Grek85] (i.e., N_D = 10¹⁴ cm^-3, A = 30 mm², L = 250 μm, I_F = 3 A, t_F = 400 ns, t_S = 40 ns). From the simulation, the 10%-90% rise time is calculated to be 15.2 ns. If just the fast part of the transient is considered, from 22% - 90%, the corresponding rise time is 3.7 ns, which is in line with the results of the simulations given in Table 8.1. It is not clear what transition time definition was used in [Grek85], particularly since the output waveform appears to be hand-drawn, rather than photographed. Similarly, Grekhov has reported a 2000 V, 2 ns device in [Grek89], yielding 1000 V/ns, but again the actual output waveform photo is not shown. For the same voltage, the optimized device of Table 8.1 indicates a 10%-90% rise time of 5.5 ns.

Figure 8.8 - Simulation results for the diode and circuit conditions in [Grek85].

Also, Figure 8.8 suggests that the value of Q_-/Q₊ of 0.71, calculated from the values given in [Grek85] is too low, as additional charge is removed from the diode after the input voltage has reached 1700 V. In other words, the voltage ramp time could have been increased to Q_-/Q₊ = 1. This simulation result tends to support the use of equation (8.41), and agrees with [Belk94].

The simulated results are in better agreement with the recent experimental results reported in [Foci96]. A rise time of approximately 5 ns is reported for a voltage swing of 1700 V, for an average switching rate of 340 V/ns. Also, the reported values of storage time and I_F/I_R yield an effective lifetime of 250 ns. Both of these values agree reasonably well with the results for the 1700V device given in Table 8.1.

8.7 - Other DSRD Issues

The maximum operating voltage for a single DSRD is somewhat limited by the fact that the diode area increases very rapidly (and undesirably) with voltage. Combining equations (8.42) and (8.43) shows that

(8.45)

whereas the desirable increase in storage time t_S is much slower:

(8.46)

For this reason, at higher voltages it may be advantageous to use multiple series-connected DSRDs rather than a single device. Belkin and Shulzchenko [Belk94] used this approach to obtain 6 kV pulses, with four lower-voltage DSRDs connected in series. This approach also has the advantage that higher middle layer dopings can be used, which makes device fabrication easier.

8.8 - Conclusion

In this section, the evolution of the carrier distributions in p⁺sn⁺ diodes during the forward transient has been considered. A critical current density, J₀, has been derived. For J >> J₀, a p⁺sn⁺ diode will behave as a pin diode, with significant charge injection at both junctions. For J << J₀, significant charge injection will occur only at the pn junction for times t < t_di. For t > t_di, carriers will be injected by both junctions. Interestingly, doping levels in the middle layer (typically 10¹⁴ cm^-3) can be orders of magnitude less than the forward steady state carrier concentrations (typically > 10¹⁶ cm^-3), and yet can dramatically affect the evolution of the carrier distributions.

The critical current J₀ has been shown to be an important parameter in the design of drift step recovery diodes. To minimize the ramp voltage, J_F should be less than J₀. Also, knowledge of J₀ allows an estimate of the maximum usable stored charge in a DSRD. This results in a much more comprehensive design theory for DSRDs than that which was previously available. This parameter should prove useful in the design of several other high-power devices that rely upon transient forward biasing, or reversible injection control.