Chapter 6 - Fabrication Method for WFSRD Devices

6.1 - Introduction

As noted in Figure 5.21, the device parameters chosen for fabrication are:

• N_S1 = 10¹⁷ cm^-3
• N_S2 = 10¹⁷ cm^-3
• N_B = 1.5 x 10¹⁴ cm^-3, p-type
• λ = 30.6 μm
• L = 150 μm
• A = 1.35 mm²

Unfortunately each one of these values falls outside the normal ranges of values typically encountered in a VLSI fab. The surface dopings are quite low. Usually, one wants them to be as high as possible to ensure a good ohmic contact. As for N_B, lightly-doped p-type substrates are generally harder to obtain than lightly-doped n-type substrates. The value of λ given is very, very long compared to normal VLSI standards for diffusion. (Values on the order of 0.1 μm are more common). Lastly, the thickness L is quite thin, compared to standard wafer thicknesses.

6.2 - General Approach

Three general methods were considered for fabrication. The first approach consisted of thinning a standard wafer with a background doping of N_B down to the desired device length of 150 μm, and diffusing in the remaining dopants. The primary disadvantages of this approach were that the thin wafer might complicate handling and yield, and that the high value of λ would require a very long time in a very hot diffusion furnace (approximately 10 days at 1250 °C). The advantages were that the thinning process was relatively inexpensive (US$110/wafer), and the diffusion could be done in-house with existing equipment at Carleton.

The second possible approach was the use of variable-dopant epitaxy to grow the exact profile desired on a thick conducting substrate. However, this would require a relatively thick (but not unheard of) epitaxial growth. Also, obtaining reasonable control of doping at 10¹⁴ cm^-3 levels would require a large amount of experimentation. For these reasons, quotes for performing this growth commercially (at Lawrence Semiconductor Research Laboratory, Inc.) proved to be expensive (US$2750 setup, plus $175/wafer). The possibility of performing this epitaxy in-house on Carleton's AET RX rapid thermal CVD system existed, however, at the time this thesis began, this equipment was brand new and not yet operational, and represented relatively untried technology.

Both of these approaches yield essentially one-dimensional structures. More complex schemes, involving selectively thinning a thick substrate were also considered. However, endpoint detection in thinning etches would be problematic. Also, the increased dimensionality is undesirable, as it would likely introduce undesired parasitic effects.

For these reasons, the first approach (thinning and long diffusion) was chosen.

6.3 - Substrate Preparation and Dopant Implantation

By happy coincidence, wafers with almost precisely the desired value of N_B were available from a surplus-wafer broker. Furthermore, these wafers were float-zone refined rather than Czochralski-refined, which is highly desirable for high-voltage devices. Float-zone material tends to produce devices with higher breakdown voltages, due to lower oxygen and other impurity content [Ghan83]. (The Czochralski refining process is performed in a quartz crucible, which leaches some oxygen into the molten silicon. Float-zone refining isolates the molten portion of the silicon ingot from contact with any crucible.)

The complete wafer specifications were as follows: Prime Grade, <100>, Boron-doped, 75-95 Ω-cm, float zone, 4 inch diameter, two standard flats, polysilicon backside, 510-540 μm thickness, made by Wacker-Siltronic, US$14. Twenty-five wafers were purchased.

To thin the wafer to the required 150 μm thickness, fifteen wafers were sent to Virginia Semiconductor for chemi-mechanical polishing (CMP). Only eight wafers survived the process, due to the thinness. The others shattered. Upon their return, the eight wafers were cleaned in Caro's acid (1 litre of sulfuric acid at 100 C, mixed with 100 mL of 30% H₂O₂) for ten minutes, and rinsed in de-ionized water.

At this point, six wafers (designated "A" to "F") were sent to Implant Center Inc, to implant the remaining dopants. A dose of 2.7 x 10¹⁴ cm^-2 of boron was implanted with a moderate energy of 80 keV on one side of each wafer, and a similar dose of phosphorus on the opposite side. The dose, Q, is related to N_S and through the relationship:

(6.1)

For N_S = 10¹⁷ cm^-3 and λ = 30.6 m, Q_impl = 2.7 x 10¹⁴ cm^-2. The total cost was very low, approximately US$130. One wafer ("B") broke during implantation, due to the wafer's thinness.

After the wafers were returned from implantation, one wafer (designated "A") was cleaned in Caro's acid. Apparently due to thermal shock, the wafer broke into two roughly equal-size pieces. However, as it had been the intention to break the wafer into several pieces at a slightly later stage, this breakage did not present a significant problem and processing continued with this wafer.

6.4 - Dopant Drive-In Diffusion

The dopants introduced by the implants were redistributed to obtain the desired values of N_S1, N_S2, and λ by using a drive-in diffusion. However, as noted earlier, the large value of requires a very long and hot diffusion. Simulations on the Suprem III simulator indicated that to obtain the desired values, a drive-in time of approximately 180 hours was required if a temperature of 1250 °C was used. (This temperature represented the maximum usable temperature of the quartz tubes that were available.) This long diffusion raises two potential problems: that of dopant suck-out, and impurity diffusion. Dopant suck-out occurs when the dopants evaporate out of the silicon wafer, or diffuse into the surface film. Impurity diffusion occurs when temperatures are high enough that impurities (like sodium) can diffuse through the furnace quartz tube and enter the wafer.

The first problem was addressed by adding an oxide layer on the wafer "A" to seal in the dopants. The "LOTOX" (low-temperature oxide) was added by placing the "A" wafer in the furnace in an oxygen atmosphere at 405 °C for 15 minutes. Judging from the gold color of the deposited oxide, the oxide thickness was about 0.2 μm. Suprem III simulations indicated that this would be sufficient to contain most of the dopants. (A standard pre-furnace RCA clean was performed before the LOTOX deposition.)

After the Lotox deposition, the wafer "A" was broken into ten smaller, roughly equal-size pieces designated "A0" to "A9". These pieces were cleaned in a standard HCl-H₂O₂ mixture (chosen so as not to etch the protective oxide), followed by a brief 5% HF dip. Pieces "A1" to "A9" were then placed into the furnace for the drive-in. The furnace operated at 1250 °C, with a 2% oxygen, 98% nitrogen atmosphere. (The nitrogen was chosen since it is relatively inert, and the oxygen prevented any nitride formation on the wafer surface). At twenty-two hours intervals, approximately, the wafer pieces were removed from the furnace, and the furnace tube was gettered with HCl for one hour, at 1250 °C. After each gettering, one wafer piece was removed, and the remainder were reloaded into the furnace. In this manner, pieces with drive-in times of approximately 23 hr, 44 hr, 65 hr, 86 hr, 107 hr, 128 hr, 149 hr, 170hr, and 199 hr were obtained, corresponding to A1 to A9, respectively. This was done in order to calibrate the drive-in process, relative to the SUPREM simulations. This process took about 10 working days. On weekends, the wafer boat was moved to the end of the furnace tube, and the temperature was dropped to 1000 °C, with a nitrogen purge. This effectively halted the drive-in, on weekends. (This measure was taken as a precaution against power outages, or other equipment problems which might arise over the weekend, when technicians were not present.)

Wafer pieces "A5" to "A9" were sent to Solecon Laboratories Inc. for spreading resistance measurements, so that the doping profiles could be examined. The results of these measurements are shown in Figure 6.1, in doping-concentration form rather than in raw resistance measurements. (The resistance-to-doping calculation was performed by Solecon.)

Figure 6.1 indicates that both A8 and A9 have nearly the ideal doping profile. The only significant deviation is the 30% lower-than-expected surface concentrations. Evidently, some dopant evaporated, or was "sucked-out" into the oxide layers. This should not have a significant impact on device operation, since the active region is the lightly-doped area around the junction. (However, relatively poor forward-bias conduction can be expected, due to poor ohmic contacts.)

Figure 6.1 - Doping profile as a function of drive-in time.

As a result of the drive-in, approximately 0.7 μm of oxide coated the wafer pieces. This was removed by etching the wafers in a 10% HF solution for approximately 35 minutes. (The endpoint of an oxide etch can be determined by observing when the silicon surface becomes hydrophobic.)

6.5 - Lifetime Killers

At this point, the fabrication sequence branched into two parts. One portion of wafer A.8 proceeded directly to metallization. A second portion, redesignated "A8.PT.850", had lifetime-killers (platinum) introduced, and then proceeded to metallization.

The platinum impurity centers were introduced into A8.PT.850 by dipping the wafer into undiluted Emulsitone Platinumfilm, a spin-on dopant source. The wafer then underwent a four hour, 850 °C, oxygen atmosphere diffusion to drive-in the platinum. Surface oxide was removed with a 10% HF solution.

6.6 - Metallization

Both A.8 and A8.PT.850 followed the same metallization steps.

The silicon surfaces were cleaned with a 2 minute, 900 V, 100 W sputter etch in 8 milliTorr of argon, to remove any oxide that had grown during the time since the HF etch, or indeed any other surface contamination. All sputtering was performed using a Materials Research Corporation 8620 diffusion-pumped multi-target system.

A chromium target was pre-sputtered by a 3 minute, 1.25 kV, 100 W etch in 8 milliTorr of argon. The wafer piece was then sputtered with the chromium for 20 minutes, at the 1.35 kV, 100 W, 8 milliTorr argon settings. Identical pre-sputtering and sputtering steps were then performed with a gold target. This produced a 6000 Å thick gold layer, bonded to the silicon surface with a 1000 Å thick chromium adhesive layer. The silicon piece was then flipped, and the process repeated, so that identical metallization existed on both sides of the wafer.

Gold was used as the top metal to ensure that the diode could be easily hand-soldered to.

A photomask was generated on a 2.5" 2.5" glass substrate (designated CU-170-01). The pattern consisted of 45 mil 45 mil squares (representing the desired metallization) on a 50 mil grid (1 mil 25 m). A positive photoresist (HPR-504) was applied to one side of the wafer, and was developed. The exposed metallization was removed with a 60 minute, 900 V, 100 W, 8 milliTorr argon sputter etch. The excess photoresist was then removed using acetone and Microstrip 2001. It was found that a black residue (presumably charred photoresist) remained on the metal surface despite the use of the photoresist strippers. This was removed with the gentle use of a cotton swab.

A dry etch, rather than a wet etch, was used to remove the excess metallization in the belief that a dry etch would introduce fewer contaminants, such as potassium, which might have deleterious effects on the breakdown voltage.

To reduce sputtering damage, and to improve the metallization adhesion, the wafer underwent a 15 second, 450 °C rapid thermal anneal (RTA).

A Tempress diamond scriber was used to scribe "A8" and "A8.PT.850" into individual devices (designated "A8.n" and "A8.PT.850.n", respectively, where n is a number). These devices where then separated by running a roller over the wafer surface, cleaving the devices along the scribe lines.