Chapter 2 - Review of Diode Reverse Transient Physics

2.1 - Introduction

It is well known that when the current through a diode is reversed from forward bias to reverse bias the voltage across the diode does not change instantaneously from a positive voltage to a negative voltage, due to the stored charge in the diode junction. Typical current transients for the circuit of Figure 2.1 are shown in Figures 2.2a and 2.2b. The diode structure can be designed to tailor the reverse recovery transient. For instance, step recovery diodes are designed to achieve a long storage time, ts, and an extremely short fall time, t_R. In contrast, power rectifiers are generally designed to minimize the total length of the reverse recovery transient, t_RR = t_S + t_R and to minimize t_S/t_R.

Figure 2.1 - Reverse recovery test circuit

The ubiquitous high voltage power rectifier and the step-recovery diode (SRD) share a common structure, that of the p+ i n+ (or just "pin") diode. The ideal pin diode consists of an intrinsic layer sandwiched between a heavily doped p-type ("p+") region and a heavily doped n-type ("n+") region. In practice this is difficult to achieve, so a psn diode is used, where "s" represents the lightly-doped middle layer, which can be p or n-type, sandwiched between the p+ and n+ regions. Both epitaxial structures (Figure 2.3) and diffused structures (Figure 2.4) are common.

Figure 2.2a - Ideal reverse recovery transients for a step recovery diode.

Figure 2.2b - Ideal reverse recovery transients for a power rectifier.

Figure 2.3 - Typical epitaxial diode structure

Figure 2.4 - Typical diffused diode structure

Despite the similar underlying structures in the SRD and the power rectifier, these two devices have developed as separate areas of study. This is due to two factors. First, as will be explained later, the conditions necessary to achieve the fast-transition characteristic of conventional SRDs require a relatively narrow s-layer, typically several microns. In contrast, power rectifiers are required to support large reverse voltages (i.e. hundreds of volts), which demands an s-layer width of several tens of microns. Secondly, the fast transition (short t_R) that the SRD is designed to achieve is generally unwanted in power rectifier applications. Sudden current transitions can lead to large inductive voltages in power circuits. Also, the entire reverse recovery transient is undesirable in power applications, as it is a source of power loss. As a consequence, considerable effort has been expended by device designers to suppress the possibility of SRD-like fast switching in power rectifiers by minimizing t_RR and, within that constraint, maximizing t_R. (For examples, see [Amem82], [Coop83], [Shim84], [Howe88], [Mori92], and [Mehr93]).

Virtually no effort has been spent considering the possibility of optimizing power rectifier structures to achieve the opposite behavior; that is SRD-like switching behavior for other applications, such as in high-voltage pulse generators. Commercially available SRDs with sub-nanosecond transition times are generally not available with breakdown voltages of more than 100V. Experimental evidence presented in Chapter 3 suggests that it is possible to design power rectifiers that can switch several hundreds of volts into a 50 Ω load in approximately 1 ns. Chapters 5 to 7 of this thesis investigate this possibility.

2.2 - Review of Power Diode Switching Principles

2.2.1 - Principles of Power Rectifier Operation - pin Diodes

Pin and psn diodes with abrupt junctions have been extensively studied in the literature. This section summarizes the essential characteristics of pin diodes, and largely follows the pioneering work of Benda and Spenke [Bend67] (as do Sections 2.2.2 and 2.2.3).

Figure 2.5 shows an ideal pin diode structure, which will be considered here. For the purpose of illustrative calculations, the following conditions will be assumed:

τ = 500 ns

d = 30 μm

μ_n = 1350 cm²/Vs

μ_p = 480 cm²/Vs

J_F = 200 mA/mm²

In forward bias, it can be shown [Bend67] that the carrier distribution in the quasi-neutral middle layer can be written as

(2.1)

Figure 2.5 - pin doping structure and carrier densities

This expression is exact for pin diodes and approximate for psn diodes. Since, by definition, the middle region of the pin diode is under high injection, the carrier concentrations are approximately equal, that is

(2.2)

The lifetime in (2.1) is the high-level ambipolar lifetime [Ghan77],

(2.3)

and the diffusion length L_d is

(2.4)

where D is the high-level ambipolar diffusion constant, given by

(2.5)

Benda and Spenke have also analytically solved the time evolution of the carrier distribution for a reverse transient, for the time when the middle region is still entirely quasi-neutral. The exact solution is lengthy and of little interest itself, but its solution is plotted for several different instants in Figure 2.6. The solution at t = 0 reduces to equation (2.1). The key observation relating to this thesis is that the carrier concentration falls to zero at the p+ i junction first, and much later at the i n+ junction. This can be seen analytically by noting that the current at a p+ i junction is carried almost entirely by holes, and that while quasi-neutrality holds, no significant electric field can develop, so that

(2.6)

and similarly

(2.7)

It is also evident that

(2.8)

Consideration of equations (2.2), (2.6), (2.7), (2.8) then gives

(2.9)

Since D_n>> 3D_p, the slope of the carrier concentration at x = -d must be three times larger than that at x = +d to satisfy (2.9); hence the concentration will fall to zero sooner at x = -d. This is clearly seen in Figure 2.6.

Once the charge distribution predicted by the analytical expression becomes negative, a space-charge region will develop. This space charge is maintained by mobile carriers in the intrinsic region, rather than by fixed ionized donors or acceptors. The assumption of quasi-neutrality can no longer be maintained after this time, and an exact analytical treatment is not available.

Figure 2.6 - Charge Removal in the i-Layer.

Benda and Spenke have analyzed the development of the space-charge regions by assuming that the boundary between the space charge regions and the quasi-neutral region in the intrinsic layer is very sharp, that is, there is a sudden discontinuous jump between the very small carrier concentration in the space-charge region and the very high quasi-neutral concentration. This concept is illustrated in Figure 2.7. The movement of these two boundaries can then analyzed by assuming a constant reverse current, I_R. If one neglects recombination, and approximates the initial carrier concentration with a constant average concentration navg, it is straightforward to show that the right and left boundaries, x = -a_l(t) and x = +a_r(t), move with the velocities

(2.10)

and

(2.11)

respectively. Hence the space-charge region at the p+ junction expands approximately three times as fast as the one at the n+ junction, since μ_n/μ_p>> 3.

Figure 2.7 - Schematic illustration of carrier removal [Benda67]

2.2.2 - Principles of Power Rectifier Operation - psn Diodes

The presence of light doping in the middle layer of the psn diode affects the spatial growth rate of the space-charge regions only minimally, but it has a strong influence on the voltage development in these space-charge regions. For instance, if the doping is n-type, the space charge at the p+ n junction can be composed of the fixed ionized donors, rather than mobile charge. When this occurs, the voltage at this junction develops as V ∝ (-d + a_l(t) )². In contrast, if the doping is p-type, a high-low junction exists at x = -d. The space-charge must then be composed of mobile holes. Furthermore, this mobile hole concentration must be larger than the acceptor concentration, if a positive space charge is to be maintained. However, since

(2.12)

and since i_R falls and E(x) rises as the reverse transient progresses, p(x) must fall rapidly. (Neglecting diffusion current in (2.12) is generally justified, see Appendix I of [Benda67] for details.) However, p(x) must remain larger than n_A in order for a positive space charge to exist. Thus if n_A is large, p(x) will asymptotically approach nA, and this region will act as an ohmic resistance. Then V ∝ (-d + a_l(t) ), so the voltage develops much more slowly than in the previous case. Whether or not this occurs depends on the relative sizes of p(x) and n_A. If n_A is very small, an ohmic region will develop very late into the transient, where the current is very low, so this effect may not be visible.

The results of this section and the previous one in terms of the reverse recovery transient can be summarized as follows:

1. Space charge develops at the p+ junction before it does at the n+ junction.

2. The space charge region widens more rapidly at the p+ junction than it does at the n+ junction.

3. Voltage develops much more slowly at p+ p and n n+ junctions than at p+ n and

p n+ junctions.

These facts allow one to predict the relative differences between ps_pn and ps_nn diodes. In the ps_pn rectifier, the space-charge region (or "SCRs") develops first at the p+ p junction, so initially the voltage across the diode develops very slowly. Later, a space-charge region will develop at the p n+ junction. Then, the voltage across the diode will increase moderately quickly. This is depicted in Figure 2.8.

Figure 2.8 - Reverse voltage development in a ps_pn rectifier.

In the ps_nn rectifier, the space-charge region develops first at the p+ n junction, so initially the voltage across the diode develops very rapidly. However, since the same amount of charge must be removed as in the case of the ps_pn rectifier, the voltage development will taper off and develop a long "tail". This is depicted in Figure 2.9.

Figure 2.9 - Reverse voltage development in a ps_nn rectifier.

This means that the ps_pn rectifier will have a short t_RR and a short t_R. Conversely, the ps_nn rectifier will have a long t_RR and a "softer" transient waveform, which as explained earlier, is desirable in most power rectifier circuits. For this reason, almost all modern commercially available power rectifiers are of the ps_nn type. Furthermore, it is easier to achieve high breakdown voltage in ps_nn rectifiers, since surface inversion can occur in the middle p-layer of ps_pn rectifiers [Grov65]. ps_nn rectifiers also have sharper breakdown "knees" than ps_pn rectifiers [Ghan77].

Before the widespread use of epitaxy, the only feasible method of rectifier production was diffusion. Thus older, obsolete diodes specified as ultra-fast rectifiers may use the ps_pn structure since, as noted above, it results in shorter t_RR times for an identical amount of stored charge relative to a ps_nn structure. However, the modern approach is to use a ps_nn structure with abrupt epitaxial boundaries, which reduces the total stored charge for a given forward current [Coop83]. Thus using epitaxy reduces both t_R and t_S, whereas using diffused ps_pn structures reduces t_R but increases t_S.

2.2.3 - Principles of Power Rectifier Operation - Diffused Diodes

The diffused rectifier will show a combination of the characteristics described in the previous two sections. Since the doping gradually varies from a very high level to a very low level near the junction, the edge of the swept-out region will initially be in the heavily doped region, and an ohmic region will develop as described in Section 2.2.2. A small voltage will be built up across this ohmic region. As the edge of the swept out region approaches the junction, the doping level will fall, and the situation will be more akin to the intrinsic doping case discussed in Section 2.2.1. At this time, a space charge region will develop, and the voltage will rapidly increase. A much more detailed discussion can be found in [Bend68].

Thus, a period of charge removal with little voltage buildup will be followed by a period of very rapid voltage buildup. This is in fact the sequence desired for a step recovery diode, although this mode of operation has not been exploited previously in SRDs.

2.3 - Review of Conventional Step Recovery Diode Switching Principles

As noted earlier, although SRDs share the same basic structure as power rectifiers, there is a difference of scale: the i-layer is generally more than an order of magnitude smaller for an SRD. In practice, this means that the boundary between the space-charge regions and the quasi-neutral regions can not be considered as abrupt. Instead, they are sloped, and the two sloped boundaries quickly overlap to form an approximately triangular carrier distribution, as shown in Figure 2.10. The following analysis follows the analysis presented by Roulston [Roul90].

Figure 2.10 - Carrier density and net charge evolution in an SRD [Roul90]

Figure 2.10 also shows the approximate net charge distribution in an SRD as the transient progresses. On the left side, the positive charge density can be estimated using

(2.13)

The assumption has been made that the electric fields are high enough that the hole velocities are saturated. Similarly, on the right side the electron density is

(2.14)

If the further assumptions are made that the space-charge regions begin to expand simultaneously, and that when the two space-charge regions overlap the current is still approximately J_R (which is characteristic of a good SRD), then the total voltage when the space-charge regions overlap can be estimated by using Poisson's equation. This gives:

(2.15)

The left space-charge region is assumed to have expanded at the same rate as the right space-charge region, meaning that they meet at x = 0.5 W.

The fast transition characteristic of the SRD begins when the two space-charge regions overlap. At this moment, almost no free charge remains in the middle region to be evacuated, and the electric field "snaps" to support the final voltage. Since the voltage development during the charge evacuation stage is comparatively slow, it is important that V_RAMP << V_R for the transient to approach to ideal rectangular SRD waveform.

2.4 - Difficulties with High Voltage Step Recovery Operation

As noted earlier, the voltage development in the pspn rectifier is initially gradual, which is followed by a sudden rapid increase, similar in concept to the operation of an SRD. The voltage at which this occurs can be estimated from (2.15). However, since W must be large in power rectifiers to sustain a high breakdown voltage, and V_RAMP ∝ W², it is difficult to design high voltage SRDs, at least according to the theory presented thus far.

Baliga [Bali87] reports that the breakdown voltage of an abrupt punch-through psn structure, BV_pt, can be estimated using

(2.16)

and

(2.17)

where W is the width of the middle layer, Ec is the critical field at which avalanche breakdown occurs, N is the doping of the middle layer, and K is a empirical constant given by:

(2.18)

If one substitutes (2.17) into (2.16), and takes the derivative of (2.16) with respect to N, one can calculate the optimum value of N for a given W that will maximize BV_pt. This yields:

(2.19)

Substituting (2.17) and (2.19) into (2.16) yields an expression for BV_pt in terms of the middle layer width:

(2.20)

Punch-through diodes involve a trade-off between doping and width. For a given breakdown voltage, a punchthrough diode has a narrow middle layer, which improves forward conduction, but it also has lighter doping, which can be more difficult to fabricate than a non-punchthrough diode. Thus in practice, the optimum value may not be used.

Ghandi [Ghan77] reports that for a non-punchthrough abrupt pin structure, the breakdown voltage BV_non, in volts, can be related empirically to the depletion width by

(2.21)

Equations (2.15), (2.20) and (2.21) are compared in Figure 2.11. For the purposes of equation (2.15) a current density of 6 A/mm² has been assumed. (This current density corresponds to a 300V transient into a 50 Ω load, with a 1 mm² diode.) For reasons noted above, the actual breakdown voltage will fall between BV_pt and BV_non. Figure 2.11 clearly shows that V_RAMP rapidly becomes a significant portion of the breakdown voltage. SRD are typically either specified in terms of the 20% to 80% or the 10% to 90% transition time, so it is important to keep V_RAMP < 0.2 BV. For the optimum punchthrough diode, V_RAMP = 0.2 BV at BV = 200 V. Beyond this point on the graph, the breakdown voltages rise almost linearly, but V_RAMP rises quadratically, so higher voltage SRDs based on the abrupt-psn structure rapidly become impractical. For instance, for a diode designed to operate at 300 V, and having a breakdown voltage of 500V, no fast transient is predicted at all.

Figure 2.11 - A comparison of ramp voltage V_RAMP and corresponding breakdown voltages for punchthrough and non-punchthrough pin structures.

The curve for V_RAMP in Figure 2.11 has been plotted assuming a constant cross-sectional area, however equation (2.15) apparently offers the possibility of reducing V_RAMP for high voltage structures by increasing A and hence reducing J_R. Unfortunately, this leads to an increased parasitic capacitance, which is highly undesirable. This issue will be discussed in later chapters.

Perhaps the best illustration of the difficulty of building step recovery diodes with high breakdown voltages is to simply survey the commercial offerings, as was done in Table 1.1. This table clearly shows the increase in transition rates at higher voltages.